1. Field of the Invention
The present invention generally relates to a thin film magnetic memory device. More particularly, the present invention relates to a thin film magnetic memory device including magnetic memory cells whose electric resistance value varies according to the level of storage data written by a magnetic field produced by a data write current.
2. Description of the Background Art
An MRAM (Magnetic Random Access Memory) device has attracted attention as a memory device capable of non-volatile data storage with low power consumption. The MRAM device is a memory device that stores data in a non-volatile manner using a plurality of thin film magnetic elements formed in a semiconductor integrated circuit and is capable of random access to each thin film magnetic element.
In particular, recent announcement shows that the performance of the MRAM device is significantly improved by using thin film magnetic elements having a magnetic tunnel junction (MTJ) as memory cells. The MRAM device including memory cells having a magnetic tunnel junction is disclosed in technical documents such as xe2x80x9cA 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cellxe2x80x9d, ISSCC Digest of Technical Papers, TA7.2, February 2000, and xe2x80x9cNonvolatile RAM based on Magnetic Tunnel Junction Elementsxe2x80x9d, ISSCC Digest of Technical Papers, TA7.3, February 2000.
FIG. 23 is a schematic diagram showing the structure of a magnetic memory cell having a magnetic tunnel junction (hereinafter, also simply referred to as xe2x80x9cMTJ memory cellxe2x80x9d).
Referring to FIG. 23, the MTJ memory cell includes a magnetic tunnel junction MTJ having its resistance value varying according to the storage data level, and an access transistor ATR. The access transistor ATR is formed from a field effect transistor (FET), and is coupled between the magnetic tunnel junction MTJ and the ground voltage Vss.
For the MTJ memory cell are provided a write word line WWL for instructing a data write operation, a read word line RWL for instructing a data read operation, and a bit line BL serving as a data line for transmitting an electric signal corresponding to the storage data level in the data read and write operations.
FIG. 24 is a conceptual diagram illustrating the data read operation from the MTJ memory cell.
Referring to FIG. 24, the magnetic tunnel junction MTJ has a magnetic layer FL having a fixed magnetic field of a fixed direction (hereinafter, also simply referred to as xe2x80x9cfixed magnetic layer FLxe2x80x9d), and a magnetic layer VL having a free magnetic field (hereinafter, also simply referred to as xe2x80x9cfree magnetic layer VLxe2x80x9d). A tunnel barrier TB formed from an insulator film is provided between the fixed magnetic layer FL and the free magnetic layer VL. According to the storage data level, either a magnetic field of the same direction as that of the fixed magnetic layer FL or a magnetic field of the direction different from that of the fixed magnetic layer FL has been written to the free magnetic layer VL in a non-volatile manner.
In the data read operation, the access transistor ATR is turned ON in response to activation of the read word line RWL. As a result, a sense current Is flows through a current path formed from the bit line BL, magnetic tunnel junction MTJ, access transistor ATR and ground voltage Vss. The sense current Is is supplied as a constant data read current from a not-shown data read circuit.
The electric resistance value of the magnetic tunnel junction MTJ varies according to the relative relation of the magnetic field direction between the fixed magnetic layer FL and the free magnetic layer VL. More specifically, when the fixed magnetic layer FL and the free magnetic layer VL have the same magnetic field direction, the magnetic tunnel junction MTJ has a smaller resistance value as compared to the case where both magnetic layers have different magnetic field directions.
Accordingly, in the data read operation, a voltage drop at the magnetic tunnel junction MTJ due to the sense current Is varies according to the magnetic field direction stored in the free magnetic layer VL. Thus, by starting supply of the sense current Is with the bit line BL precharged to a high voltage, the storage data in the MTJ memory cell can be read by sensing a change in voltage level on the bit line BL.
FIG. 25 is a conceptual diagram illustrating the data write operation to the MTJ memory cell.
Referring to FIG. 25, in the data write operation, the read word line RWL is inactivated, so that the access transistor ATR is turned OFF. In this state, a data write current for applying a magnetic field to the free magnetic layer VL is applied to the write word line WWL and the bit line BL. The magnetic field direction of the free magnetic layer VL is determined by combination of the respective directions of the data write current flowing through the write word line WWL and the bit line BL.
FIG. 26 is a conceptual diagram illustrating the relation between the respective directions of the data write current and the magnetic field in the data write operation.
Referring to FIG. 26, a magnetic field Hx of the abscissa indicates the direction of a magnetic field H(WWL) produced by the data write current flowing through the write word line WWL. A magnetic field Hy of the ordinate indicates the direction of a magnetic field H(BL) produced by the data write current flowing through the bit line BL.
The magnetic field direction stored in the free magnetic layer VL is updated only when the sum of the magnetic fields H(WWL) and H(BL) reaches the region outside the asteroid characteristic line shown in the figure. In other words, the magnetic field direction stored in the free magnetic layer VL is not updated when a magnetic field corresponding to the region inside the asteroid characteristic line is applied.
Accordingly, in order to update the storage data of the MTJ memory cell by the data write operation, a current must be applied to both the write word line WWL and the bit line BL. Once the magnetic field direction, i.e., the storage data, is stored in the magnetic tunnel junction MTJ, it is retained therein in a non-volatile manner until another data read operation is conducted.
The sense current Is flows through the bit line BL in the data read operation. However, the sense current Is is generally set to a value that is smaller than the data write current by about one or two orders of magnitude. Therefore, it is less likely that the storage data in the MTJ memory cell is erroneously rewritten by the sense current Is during the data read operation.
FIG. 27 is a diagram showing the structure of the MTJ memory cell formed on a semiconductor substrate.
Referring to FIG. 27, the access transistor ATR is formed in a p-type region PAR of a semiconductor main substrate SUB. The access transistor ATR has source/drain regions (n-type regions) 110, 120 and a gate 130. The source/drain region 110 is coupled to the ground voltage Vss through a metal wiring formed in a first metal wiring layer M1. A metal wiring formed in a second metal wiring layer M2 is used as the write word line WWL. The bit line BL is formed in a third metal wiring layer M3.
The magnetic tunnel junction MTJ is formed between the second metal wiring layer M2 of the write word line WWL and the third metal wiring layer M3 of the bit line BL. The source/drain region 120 of the access transistor ATR is electrically coupled to the magnetic tunnel junction MTJ through a metal film 150 formed in a contact hole, the first and second metal wiring layers M1 and M2, and a barrier metal 140. The barrier metal 140 is a buffer material for providing electrical coupling between the magnetic tunnel junction MTJ and metal wirings.
As described before, in the MTJ memory cell, the read word line RWL and the write word line WWL are provided independently of each other. The read word line RWL is provided in order to control the gate voltage of the access transistor ATR, and therefore a current need not be actively applied to the read word line RWL. Accordingly, for the purpose of improving the integration degree, the read word line RWL is formed from a polysilicon layer, polycide structure, or the like in the same wiring layer as that of the gate 130. In other words, an additional independent metal wiring layer is not formed for the read word line RWL.
In the data write operation, a data write current for generating a magnetic field having a magnitude equal to or larger than a predetermined value must be applied to the write word line WLL and the bit line BL. Therefore, a relatively large current must be applied to the bit line BL and the write word line WWL, and thus the bit line BL and the write word line WWL are each formed from a metal wiring.
The above-mentioned technical documents disclose the technology of forming an MRAM device, a random access memory (RAM), with such MTJ memory cells integrated on a semiconductor substrate.
FIG. 28 is a memory block diagram illustrating supply of the data write current to the MTJ memory cells arranged in rows and columns in an integrated manner.
Referring to FIG. 28, the MTJ memory cells are generally arranged in rows and columns in order to realize a highly integrated MRAM device. In FIG. 28, the MTJ memory cells are arranged in n rows by m columns (where n, m is a natural number).
As described before, the bit line BL, write word line WWL and read word line RWL are provided for each MTJ memory cell. Accordingly, n write word lines WWL1 to WWLn, n read word lines RWL1 to RWLn, and m bit lines BL1 to BLm are provided for the nxc3x97m MTJ memory cells.
In the data write operation, the data write current is applied to the write word line WWL of the selected memory cell row and the bit line BL of the selected memory cell column. For example, in order to write the data to the memory cell MC of the first row, first column, a data write current Ip is applied to the write word line WWL1 activated by a not-shown word line driver, as well as a data write current Iw is applied to the bit line BL1. It should be noted that the direction of the data write currents Ip and Iw must be controlled according to the write data level.
Accordingly, data write circuits 510 and 520 respectively set the voltages at both ends of the bit line of the selected memory cell column to different voltage levels, e.g., the power supply voltage Vcc and the ground voltage Vss. Which voltage is applied to which end of the bit line must be set according to the write data level. Thus, a magnetic field corresponding to the write data level can be applied to the selected memory cell.
A system LSI (Large Scale Integration) such as a logic-mounted memory has been developed which integrates a logic such as processor or ASIC (Application Specific Integrated Circuit) and a mass-storage random access memory (RAM) on the same semiconductor chip (semiconductor substrate).
Such a system LSI interconnects the logic with the memory such as RAM through a multi-bit internal data bus. The internal data bus is short enough as compared to a wiring on the board, and has small parasitic impedance. Therefore, significant reduction in a charging/discharging current of the internal data bus as well as high-speed signal transmission can be realized. For example, the data transfer speed that is at least one order or two orders higher than that of a general-purpose RAM can be realized. Moreover, the number of external pin terminals of the logic can be reduced as compared to the case where a general-purpose memory is externally connected to the logic.
For these reasons, the system LSI such as a logic-mounted memory significantly contributes to improved performance of the information equipments for the processing handling a massive amount of data such as three-dimensional graphic processing and image/speech processing. In a memory mounted in such a system LSI, multi-bit data must be written in parallel.
As described before, in the data write operation of the MRAM device, a data write magnetic field larger than a predetermined value must be applied, and therefore a relatively large write current is required. Accordingly, applying the MRAM device to the logic-mounted system LSI would significantly increase the current consumption since the multi-bit data is written in parallel. This may increase the power consumption and prevent an operational margin from being ensured due to the magnetic noise generated from a power supply wiring.
It is an object of the present invention to provide a thin film magnetic memory device that writes the data of a plurality of bits in parallel with a small data write current.
According to the present invention, a thin film magnetic memory device capable of writing input data of a plurality of bits in parallel includes a memory array and a plurality of write word lines. The memory array includes a plurality of magnetic memory cells arranged in rows and columns. Each of the plurality of magnetic memory cells includes a storage portion having an electric resistance value varying according to a data level that is written according to combination of first and second data write magnetic fields respectively applied by first and second data write currents. The memory array is divided into a plurality of memory blocks, and one of the plurality of memory blocks is selected in a data write operation. Each of the plurality of memory blocks includes k first bit lines respectively corresponding to the columns of the plurality of magnetic memory cells, for passing the first data write current therethrough (where k is an integer at least 2), a block selection gate for coupling first and second nodes to first and second voltages, respectively, when a corresponding one of the plurality of memory blocks is selected, and a first bit-line current switching portion for connecting the k first bit lines in series between the first and second nodes in the data write operation so that the first data write current flows through each of the k first bit lines in a direction corresponding to a respective data level of k-bit input data. The plurality of write word lines respectively correspond to the rows of the magnetic memory cells, and are selectively activated in the data write operation according to a row selection result, for passing the second data write current therethrough.
Accordingly, a primary advantage of the present invention is that the k-bit input data can be written in parallel by supplying the first data write current to the series-connected k first bit lines in the memory block selected for the data write operation (where k is an integer equal to or larger than 2). As a result, the data write current required to write a plurality of bits in parallel can be suppressed, allowing for reduced power consumption of the MRAM device as well as stabilized operation thereof due to reduced magnetic noise.
According to another aspect of the present invention, a thin film magnetic memory device capable of writing input data of a plurality of bits in parallel includes a memory array, a plurality of first bit lines, a plurality of write word lines, and a bit-line current switching portion.
The memory array includes a plurality of magnetic memory cells arranged in rows and columns. Each of the plurality of magnetic memory cells includes a storage portion having a resistance value varying according to a data level that is written according to combination of first and second data write magnetic fields respectively applied by first and second data write currents. The plurality of first bit lines respectively correspond to the columns of the plurality of magnetic memory cells, for passing the first data write current therethrough according to a column selection result. Each of the first bit lines is divided into h first sub bit lines. The plurality of write word lines respectively correspond to the rows of the magnetic memory cells, and are selectively activated in a data write operation according to a row selection result, for passing the second data write current therethrough. The plurality of write word lines is divided into h groups respectively corresponding to the h first sub bit lines, and one of the write word lines is activated in each of the h groups according to the row selection result. The bit-line current switching portion is provided for every first bit line. Each of the bit-line current switching portions couples the corresponding h first sub bit lines in series between a first node receiving the first data write current to be supplied to a corresponding one of the plurality of first bit lines and a second node receiving the first data write current from the corresponding first bit line, and the coupling of the h first sub bit lines in series between the first and second nodes is conducted so that the first data write current flows through each of the h first sub bit lines of the corresponding first bit line in a direction corresponding to a respective data level of h-bit input data to be written through the corresponding first bit line.
Accordingly, h-bit input data can be written in parallel by supplying the first data write current to the series-connected h first sub bit lines (where h is an integer equal to or larger than 2). As a result, the data write current required to write a plurality of bits in parallel can be suppressed, allowing for reduced power consumption of the MRAM device as well as stabilized operation thereof due to reduced magnetic noise.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.